PIC16F873T-04E/SO【PDF 159/218 页】IC MCU FLASH 4KX14 EE 28SOIC

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Sheet目录3889

155页 156页 157页 158页 [159页]160页 161页 162页 163页

2001 Microchip Technology Inc.

DS30292C-page 43

PIC16F87X

4.2

Reading the EEPROM Data

Memory

Reading EEPROM data memory only requires that the

desired address to access be written to the EEADR

data will be available in the EEDATA register on the

very next instruction cycle. EEDATA will hold this value

until another read operation is initiated or until it is writ-

ten by firmware.

The steps to reading the EEPROM data memory are:

Write the address to EEDATA. Make sure that

the address is not larger than the memory size

of the PIC16F87X device.

Clear the EEPGD bit to point to EEPROM data

memory.

Set the RD bit to start the read operation.

Read the data from the EEDATA register.

EXAMPLE 4-1:

EEPROM DATA READ

4.3

Writing to the EEPROM Data

Memory

There are many steps in writing to the EEPROM data

memory. Both address and data values must be written

to the SFRs. The EEPGD bit must be cleared, and the

WREN bit must be set, to enable writes. The WREN bit

should be kept clear at all times, except when writing to

the EEPROM data. The WR bit can only be set if the

WREN bit was set in a previous operation, i.e., they

both cannot be set in the same operation. The WREN

bit should then be cleared by firmware after the write.

Clearing the WREN bit before the write actually com-

pletes will not terminate the write in progress.

Writes to EEPROM data memory must also be pref-

aced with a special sequence of instructions, that pre-

vent inadvertent write operations. This is a sequence of

five instructions that must be executed without interrup-

tions. The firmware should verify that a write is not in

progress, before starting another cycle.

The steps to write to EEPROM data memory are:

If step 10 is not implemented, check the WR bit

to see if a write is in progress.

Write the address to EEADR. Make sure that the

address is not larger than the memory size of

the PIC16F87X device.

Write the 8-bit data value to be programmed in

the EEDATA register.

Clear the EEPGD bit to point to EEPROM data

memory.

Set the WREN bit to enable program operations.

Disable interrupts (if enabled).

Execute the special five instruction sequence:

Write 55h to EECON2 in two steps (first to W,

then to EECON2)

Write AAh to EECON2 in two steps (first to

W, then to EECON2)

Set the WR bit

Enable interrupts (if using interrupts).

Clear the WREN bit to disable program opera-

tions.

10. At the completion of the write cycle, the WR bit

is cleared and the EEIF interrupt flag bit is set.

(EEIF must be cleared by firmware.) If step 1 is

not implemented, then firmware should check

for EEIF to be set, or WR to clear, to indicate the

end of the program cycle.

EXAMPLE 4-2:

EEPROM DATA WRITE

BSF

STATUS, RP1

;

BCF

STATUS, RP0

;Bank 2

MOVF

ADDR, W

;Write address

MOVWF

EEADR

;to read from

BSF

STATUS, RP0

;Bank 3

BCF

EECON1, EEPGD

;Point to Data memory

BSF

EECON1, RD

;Start read operation

BCF

STATUS, RP0

;Bank 2

MOVF

EEDATA, W

;W = EEDATA

BSF

STATUS, RP1

;

BSF

STATUS, RP0

;Bank 3

BTFSC

EECON1, WR

;Wait for

GOTO

$-1

;write to finish

BCF

STATUS, RP0

;Bank 2

MOVF

ADDR, W

;Address to

MOVWF

EEADR

;write to

MOVF

VALUE, W

;Data to

MOVWF

EEDATA

;write

BSF

STATUS, RP0

;Bank 3

BCF

EECON1, EEPGD ;Point to Data memory

BSF

EECON1, WREN

;Enable writes

;Only disable interrupts

BCF

INTCON, GIE

;if already enabled,

;otherwise discard

MOVLW

0x55

;Write 55h to

MOVWF

EECON2

;EECON2

MOVLW

0xAA

;Write AAh to

MOVWF

EECON2

;EECON2

BSF

EECON1, WR

;Start write operation

;Only enable interrupts

BSF

INTCON, GIE

;if using interrupts,

;otherwise discard

BCF

EECON1, WREN

;Disable writes

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